Plug-and-play FPGA design

Network researchers need a cheap and reconfigurable solution for testing new ideas, might these be new algorithms, protocols, or entire new architectural concepts. Software-based simulations have so far been the main testing environment for network research. However as data rates of commercial communication systems has increased fast, the discrepancy between data rates that can be simulated and operational rates is constantly widening.

If we look at some tools that in the past few years have gained much popularity among network researchers we can probably infer what are their key requirements:

1) The click modular router: a software based platform running on commodity hardware that allows easy plug-and-play of a (growing) number of network element to build up a network stack

2) The NetFPGA platform: an FPGA-based reconfigurable hardware platform for running different network devices at line-rate speed (1G and 10G)

3) The OpenFlow platform: a framework that allows to control and modify the behavior of network devices that implement it.

It is clear then that we, network researchers, have been looking for:

a) a tool for testing proprietary algorithms,  protocols or architectural frameworks at line rate speed for concept proofing in realistic scenarios

b) a platform that allows reusing existing elements (either proprietary or publicly available). Although we tend to focus our work on a subset of a communication stack, we often need to implement the entire stack in order to carry out experiments. Thus an ideal platform should provide many ready-to-use ordinary and advanced elements operating at different network layers.

c) a one-fit-all platform, which can be completely configured to reproduce the behavior of any (or a large number of) network devices. As researchers move to different topics or tasks they should be able to re-use their hardware

d) a platform where protocol stacks are easy and quick to deploy and modify. We want to spend more time in the development of the idea rather than on its hardware implementation

The problem is that such features do not yet exists all in one platform. The ideal platform can be summarized in two word, we want high-level software programming running at hardware speed. Basically a click-like (1) environment able to run on a NetFPGA (2) board. Ideally as a third step, we would also like that such platform be embedded in commercial network devices, such as in OpenFlow (3), so that large testbeds can be re-programmed to run experiments.

There is a growing number of research projects in the FPGA application field that aim at realizing such ideal platforms, the most populars being: Chimpp, Cliff, CUSP and Software-Defined Silicon.

At CTVR we also have a project with a similar goal: we are investigating how can high-level synthesis design tools be embedded in an click-like architecture, to deliver an high-level software programming tool for delivering (FPGA-based) implementations running at hardware speed.

Stay tuned for updates…